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ADF4382BCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs)
| データシート | ADF4382BCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs) |
| Manufacturer | Analog Devices |
| Model | ADF4382BCCZ |
| Category | Phase-Locked Loop (PLL) Synthesizers |
| Sales Unit | 1 Tray |
| Pack Qty (pcs) | 260 |
| MOQ (pcs) | 260 |
| Order Multiple (pcs) | 260 |
| Device Package | 48-Terminal Land Grid Array [LGA] (7mm × 7mm × 1.248mm) |
| Packing Type | Tray |
| Package terminal count | 48 pins/balls |
| Package Dimensions | 7mm × 7mm × 1.248mm |
| RF output frequency range | 687.5 to 22000 MHz Complete frequency coverage using output dividers fundamental VCO is 11–22 GHz |
| Fundamental VCO frequency range | 11 to 22 GHz Fundamental octave, before output dividers |
| Output frequency range | 687.5 MHz to 22 GHz |
| Signal-to-Noise Ratio (SNR) | Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method) |
| Calibration | VCO fast calibration time < 1 μs VCO autocalibration time < 100μs |
| Phase noise floor | −156 dBc/Hz at 20 GHz |
| Features | PLL Specifications: 625 MHz maximum phase/frequency detector input frequency Multichip output phase alignment 3.3 V and 5 V power supplies ADIsimPLL™ loop filter design tool support 7 mm × 7 mm, 48-terminal LGA |
| Output Noise | PLL Specifications: -239 dBc/Hz: Normalized In-Band Phase Noise Floor |
| Reference | 4.5 GHz reference input frequency |
| Typical spurious fPFD | −90 dBc |
| Reference to output delay specifications | Adjustment step size: <1 ps |
ADF4382BCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs)
| 総重量 | 0.595 |
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