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AD9251BCPZ-65 Analog Devices Analog to Digital Converters (ADCs) - 1 Tray (260 pcs)
| Datasheet | AD9251BCPZ-65 Analog Devices Analog to Digital Converters (ADCs) - 1 Tray (260 pcs) |
| Manufacturer | Analog Devices |
| Model | AD9251BCPZ-65 |
| Category | Analog to Digital Converters (ADCs) |
| Sales Unit | 1 Tray |
| Pack Qty (pcs) | 260 |
| MOQ (pcs) | 260 |
| Order Multiple (pcs) | 260 |
| Device Package | 64-Lead LFCSP (9mm x 9mm x 0.75mm w/ EP) |
| Packing Type | Tray |
| Operating temperature range | -40 to 85 °C |
| Pin / terminal count | 64 pins / terminals |
| Nominal package body width | 9 mm |
| Nominal package body length | 9 mm |
| Conversion rate | 3 MSPS (Min.) 65 MSPS (Max.) clock rate after CLK divider AVDD=DRVDD=1.8V, 2Vp-p differential input, 1.0V reference, DCS disabled, full rated temperature |
| Resolution | 14 bits AD9251 and D13:D0 outputs nominal 14-bit ADC resolution across speed grades related AD9204/AD9231/AD9258/AD9268 are excluded |
| Channels | 2 |
| Channel Configuration | ADC channels A and B output multiplexing supported |
| Digital interface | Parallel CMOS ADC data outputs with multiplex option separate SPI configuration port |
| Features | 1.8 V analog supply operation 1.8 V to 3.3 V output supply 2 V p-p differential analog input Serial port control options Data output multiplex option Built-in selectable digital test pattern generation |
| SNR | 74.3 dBFS at 9.7 MHz input 71.5 dBFS at 200 MHz input |
| SFDR | 93 dBc at 9.7 MHz input 80 dBc at 200 MHz input |
| Bandwidth | Differential input with 700 MHz bandwidth |
| Reference | On-chip voltage reference and sample-and-hold circuit |
| Clock Features | Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider |
| Operating Modes | Energy-saving power-down modes |
AD9251BCPZ-65 Analog Devices Analog to Digital Converters (ADCs) - 1 Tray (260 pcs)
| Brutogewicht | 0.595 |
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