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ADF4368BCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs)
| Datasheet | ADF4368BCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs) |
| Manufacturer | Analog Devices |
| Model | ADF4368BCCZ |
| Category | Phase-Locked Loop (PLL) Synthesizers |
| Sales Unit | 1 Tray |
| Pack Qty (pcs) | 260 |
| MOQ (pcs) | 260 |
| Order Multiple (pcs) | 260 |
| Device Package | 48-Terminal Land Grid Array [LGA] (7mm x 7mm) |
| Packing Type | Tray |
| Package terminal count | 48 pins/balls |
| Package Dimensions | 7mm x 7mm |
| RF output frequency range | 800 to 12800 MHz Selectable divider outputs no internal doubler needed |
| Reference input frequency range | 10 to 4000 MHz TA=-40 to +105°C, 3.3 V rails 3.15–3.45 V, 5 V rails 4.75–5.25 V |
| Operating junction temperature | -40 to 125 °C Ambient operating temperature range is -40 to +105°C |
| Output frequency range | 800 MHz to 12.8 GHz |
| Wideband phase noise floor | −160 dBc/Hz at 12.8 GHz |
| Normalized in-band phase noise floor | −239 dBc/Hz: integer, −237 dBc/Hz: fractional mode |
| Output Noise | PLL specifications: Normalized 1/f phase noise floor |
| Normalized 1/f phase noise floor | −287 dBc/Hz: normalized to 1 Hz −147 dBc/Hz: normalized to 1 GHz at 10 kHz |
| PLL specifications | 625 MHz phase detector frequency integer mode 250 MHz phase detector frequency fractional mode 25-bit fixed, 49-bit combined fractional modulus 4 GHz reference input frequency Typical −95 dBc PFD spurs |
| Reference to output delay specifications | Adjustment step size: <1 ps |
| Features | 3.3 V and 5 V power supplies ADIsimPLL™ loop filter design tool support |
ADF4368BCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs)
| Brutogewicht | 0.595 |
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