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ADF4382ABCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs)
| Datenblatt | ADF4382ABCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs) |
| Manufacturer | Analog Devices |
| Model | ADF4382ABCCZ |
| Category | Phase-Locked Loop (PLL) Synthesizers |
| Sales Unit | 1 Tray |
| Pack Qty (pcs) | 260 |
| MOQ (pcs) | 260 |
| Order Multiple (pcs) | 260 |
| Device Package | 48-Terminal Land Grid Array [LGA] (7mm x 7mm x 1.25 mm) |
| Packing Type | Tray |
| Package terminal count | 48 pins/balls |
| Package Dimensions | 7mm x 7mm x 1.25 mm |
| Fundamental output frequency range | 11.5 to 21 GHz Fundamental VCO output |
| Divide-by-two output frequency range | 5.75 to 10.5 GHz Output divider set to divide by 2 |
| Divide-by-four output frequency range | 2.875 to 5.25 GHz Output divider set to divide by 4 |
| Features | Divide by 2 output frequency range: 5.75 GHz to 10.5 GHz Divide by 4 output frequency range: 2.875 GHz to 5.25 GHz Multichip output phase alignment 3.3 V and 5 V power supplies ADIsimPLL™ loop filter design tool support 7 mm × 7 mm, 48-terminal LGA |
| Signal-to-Noise Ratio (SNR) | Integrated RMS jitter at 20 GHz = 31 fs (ADC SNR method) |
| Calibration | VCO fast calibration time < 1 μs VCO autocalibration time < 100 μs |
| Phase noise floor | −156 dBc/Hz at 20 GHz |
| Output Noise | PLL specifications: −239 dBc/Hz: normalized in-band phase noise floor PLL specifications: −287 dBc/Hz: normalized 1/f phase noise floor |
| PLL specifications | 625 MHz maximum phase/frequency detector input frequency 4.5 GHz reference input frequency Typical spurious fPFD: −90 dBc |
| Reference | Reference to output delay specifications |
| Adjustment step size | <1 ps |
ADF4382ABCCZ Analog Devices Phase-Locked Loop (PLL) Synthesizers - 1 Tray (260 pcs)
| Bruttogewicht | 0.595 |
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